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A time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layout

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A time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layout

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Title: A time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layout
Author: Ng, K. A.; Chan, Pak Kwong
Copyright year: 2005
Abstract: A new time-multiplexed switched-capacitor (TM-SC)equalizer is designed on the basis of the previously reported correlated double-sampling integrator and the crosstalk reduction layout approach, which aims at improving the performance aspects on crosstalk, gain loss, 1 noise and offset. The equalizer, which operates at a single 3-V supply and has a filter bank with 4 TM channels, has been fabricated to confirm the effectiveness of the structure using a standard 0.8- m CMOS process. Index Terms—Crosstalk, equalizers, integrated circuit, layout, switched-capacitor (SC) circuit, time-multiplexed (TM) circuit.
Subject: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Type: Journal Article
Series/ Journal Title: IEEE transactions on circuits and systems
Rights: IEEE Transactions on Circuits and Systems. © 2006 IEEE. Journal can be found at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=31.
Version: Published version

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