| dc.contributor.author |
Ng, K. A. |
| dc.contributor.author |
Chan, Pak Kwong. |
| dc.date.accessioned |
2009-04-17T10:23:39Z |
| dc.date.available |
2009-04-17T10:23:39Z |
| dc.date.copyright |
2005 |
| dc.date.issued |
2009-04-17T10:23:39Z |
| dc.identifier.citation |
Ng, K. A., & Chan, P. K., (2005). A time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layout. IEEE Transactions on Circuits and Systems, 52(10), 2065-2074. |
| dc.identifier.issn |
0098-4094 |
| dc.identifier.uri |
http://hdl.handle.net/10220/4561 |
| dc.description.abstract |
A new time-multiplexed switched-capacitor (TM-SC)equalizer is designed on the basis of the previously reported correlated double-sampling integrator and the crosstalk reduction layout approach, which aims at improving the performance aspects
on crosstalk, gain loss, 1 noise and offset. The equalizer, which operates at a single 3-V supply and has a filter bank with
4 TM channels, has been fabricated to confirm the effectiveness of the structure using a standard 0.8- m CMOS process.
Index Terms—Crosstalk, equalizers, integrated circuit, layout,
switched-capacitor (SC) circuit, time-multiplexed (TM) circuit. |
| dc.format.extent |
10 p. |
| dc.language.iso |
en |
| dc.relation.ispartofseries |
IEEE transactions on circuits and systems |
| dc.rights |
IEEE Transactions on Circuits and Systems. © 2006 IEEE. Journal can be found at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=31. |
| dc.subject |
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits. |
| dc.title |
A time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layout. |
| dc.type |
Journal Article |
| dc.identifier.doi |
http://dx.doi.org/10.1109/TCSI.2005.852921 |
| dc.description.version |
Published version |
