|
Title:
|
FPGA implementation of digital filters synthesized using the frequency-response masking technique.
|
|
Author:
|
Lim, Yong Ching.; Yu, Ya Jun.; Zheng, H. Q.; Foo, Say Wei.
|
|
Copyright year:
|
2001 |
|
Abstract:
|
The effective length of a filter designed using the frequency-response masking technique is very high and requires a very large number of delay elements. In this
paper, we present some useful techniques for reducing the data transfer between the FPGA and external memory when the random logic are implemented using FPGA and the delay elements are implemented using external memory such as DRAM. |
|
Type:
|
Conference Paper |
|
Conference name:
|
IEEE International Symposium on Circuits and Systems (2001) |
|
Rights:
|
© 2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. |
|
Version:
|
Accepted version |
