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A micropower low-voltage multiplier with reduced spurious switching.

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A micropower low-voltage multiplier with reduced spurious switching.

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dc.contributor.author Chong, Kwen-Siong.
dc.contributor.author Gwee, Bah Hwee.
dc.contributor.author Chang, Joseph Sylvester.
dc.date.accessioned 2009-06-22T07:27:45Z
dc.date.available 2009-06-22T07:27:45Z
dc.date.copyright 2005
dc.date.issued 2009-06-22T07:27:45Z
dc.identifier.citation Chong, K. S., Gwee, B. H., & Chang, J. S. (2005). A micropower low-voltage multiplier with reduced spurious switching. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(2), 255-265.
dc.identifier.issn 1063-8210
dc.identifier.uri http://hdl.handle.net/10220/4643
dc.description.abstract We describe a micropower 16 16-bit multiplier (18.8 W/MHz @1.1 V) for low-voltage power-critical low speed ( 5 MHz) applications including hearing aids. We achieve the micropower operation by substantially reducing (by 62% and 79% compared to conventional 16 16-bit and 32 32-bit designs respectively) the spurious switching in the Adder Block in the multiplier. The approach taken is to use latches to synchronize the inputs to the adders in the Adder Block in a predetermined chronological sequence. The hardware penalty of the latches is small because the latches are integrated (as opposed to external latches) into the adder, termed the Latch Adder (LA). By means of the LAs and timing, the number of switchings (spurious and that for computation) is reduced from 5 6 and 10 per adder in the Adder Block in conventional 16 16-bit and 32 32-bit designs respectively to 2 in our designs. Based on simulations and measurements on prototype ICs (0.35 m three metal dual poly CMOS process), we show that our 16 16-bit design dissipates 32% less power, is 20% slower but has 20% better energy-delay-product (EDP) than conventional 16 16-bit multipliers. Our 32 32-bit design is estimated to dissipate 53% less power, 29% slower but is 39% better EDP than the conventional general multiplier.
dc.format.extent 11 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on very large scale integration (VLSI) systems
dc.rights © 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title A micropower low-voltage multiplier with reduced spurious switching.
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.description.version Published version

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