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Temperature and stress distribution in the SOI structure during fabrication

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Temperature and stress distribution in the SOI structure during fabrication

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dc.contributor.author Tan, Cher Ming
dc.contributor.author Gan, Zhenghao
dc.contributor.author Gao, Xiaofang
dc.date.accessioned 2009-06-23T01:55:39Z
dc.date.available 2009-06-23T01:55:39Z
dc.date.copyright 2003
dc.date.issued 2009-06-23T01:55:39Z
dc.identifier.citation Tan, C. H., Gan, Z., & Gao, X. (2003). Temperature and stress distribution in the SOI structure during fabrication. IEEE Transactions on Semiconductor Manufacturing, 16(2), 314-318.
dc.identifier.issn 0894-6507
dc.identifier.uri http://hdl.handle.net/10220/4654
dc.description.abstract Silicon wafer bonding technology is becoming one of the key technologies in the silicon-on-insulator (SOI) structure fabrication. However, the high-temperature heat treatment during SOI fabrication is inevitable, and the thermal stress thus induced could have an adverse effect on the device fabricated and the bonding interface. In this work, a finite-element analysis software, ANSYS, is used to study the induced mechanical stresses at the interface during the withdrawal of wafers from a high-temperature furnace. It is found that the type of insulators and the geometric dimension of the devices such as the thickness of the work layer, insulator layer, and the substrate thickness are insignificant contributors to the induced thermal stresses. Although it is expected that the furnace temperature and withdrawal velocity are the key factors in determining the mechanical stresses, for the present bonding strength of wafers via wafer bonding technology, the withdrawal velocity must be less than 100 mm/min, and under such a withdrawal velocity, the furnace temperature is also an insignificant factor with regard to the induced stress.
dc.format.extent 5 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on semiconductor manufacturing
dc.rights © 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title Temperature and stress distribution in the SOI structure during fabrication
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TSM.2003.811886
dc.description.version Published version

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