Analysis and design of power efficient class D amplifier output stages

DSpace/Manakin Repository


Search DR-NTU

Advanced Search Subject Search


My Account

Analysis and design of power efficient class D amplifier output stages

Show simple item record

dc.contributor.author Chang, Joseph Sylvester
dc.contributor.author Tan, Meng Tong
dc.contributor.author Cheng, Zhihong
dc.contributor.author Tong, Yit Chow
dc.date.accessioned 2009-06-23T05:52:54Z
dc.date.available 2009-06-23T05:52:54Z
dc.date.copyright 2000
dc.date.issued 2009-06-23T05:52:54Z
dc.identifier.citation Chang, J. S., Tan, M. T., Cheng, Z., & Tong, Y. C. (2000). Analysis and design of power efficient class D amplifier output stages. IEEE Transactions on Circuits and System-I: Fundamental Theory and Applications, 47(6), 897-902.
dc.identifier.issn 1057-7122
dc.identifier.uri http://hdl.handle.net/10220/4661
dc.description.abstract A Class D amplifier comprises a pulse width modulator and an output stage. In this paper, we analyze the power dissipation mechanisms and derive the overall power efficiency of the output stage realized using the finger and waffle layouts.We compare the relative merits of these layouts. We propose two design methodologies to determine the aspect ratios of the transistors in the output stage for optimum power efficiency (optimum for a given fabrication process, supply voltage and load resistance): 1) optimization to a single modulation index point and 2) optimization to a range of modulation indexes. For the design of an output stage with optimum power efficiency (and small IC area), we recommend optimization to a range of modulation indexes and a layout realized by the waffle structure. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype IC’s.
dc.format.extent 6 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on circuits and system-I : fundamental theory and applications
dc.rights © 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title Analysis and design of power efficient class D amplifier output stages
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/81.852942
dc.description.version Published version

Files in this item

Files Size Format View Description
Analysis and De ... mplifier Output Stages.pdf 336.8Kb PDF View/Open Published version

This item appears in the following Collection(s)

Show simple item record


Total views

All Items Views
Analysis and design of power efficient class D amplifier output stages 825

Total downloads

All Bitstreams Views
Analysis and Design of Power Efficient Class D Amplifier Output Stages.pdf 693

Top country downloads

Country Code Views
United States of America 216
China 59
Singapore 48
India 44
Taiwan 24

Top city downloads

city Views
Mountain View 126
Singapore 47
Beijing 27
Taipei 17
Kiez 11