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Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications

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Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications

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dc.contributor.author Sia, Choon Beng
dc.contributor.author Ong, Beng Hwee
dc.contributor.author Chan, Kwok Wai
dc.contributor.author Yeo, Kiat Seng
dc.contributor.author Ma, Jianguo
dc.contributor.author Do, Manh Anh
dc.date.accessioned 2009-06-23T06:39:24Z
dc.date.available 2009-06-23T06:39:24Z
dc.date.copyright 2005
dc.date.issued 2009-06-23T06:39:24Z
dc.identifier.citation Sia, C. B., Ong, B. H., Chan, K. W., Yeo, K. S., Ma, J. G., & Do, M. A. (2005). Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications. IEEE Transactions on Electron Devices, 52(12), 2559-2567.
dc.identifier.issn 0018-9383
dc.identifier.uri http://hdl.handle.net/10220/4663
dc.description.abstract A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-µm RFCMOS technology, experimental results in this paper reveal that inductors’ core diameters must be adequately large, more than 100 µm, to ensure high quality factor characteristics and their conductor spacing should be minimal to obtain larger per unit area inductance value. A novel design methodology which optimizes the conductor width of inductors allows alignment of their peak quality factor to the circuit’s operating frequency, enhancing the gain, input/output matching characteristics and noise figure of a giga-hertz amplifier.
dc.format.extent 9 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on electron devices
dc.rights © 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TED.2005.859638
dc.description.version Published version

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