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Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment

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Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment

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Title: Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment
Author: Seah, Lionel Siau Hing; Yeo, Kiat Seng; Ma, Jianguo; Do, Manh Anh
Copyright year: 2001
Abstract: The effective channel length L-eff and total external series resistance R-TOTEXT of deep submicron lightly doped drain (LDD) pMOSFETs, operating in a Bi-MOS hybrid-mode environment, have been modeled as functions of bias and temperature. The accuracy of the device threshold voltage used in the L-eff and R-TOTEXT extraction routine is discussed. The proposed models have been verified for temperature ranging from 223 K to 398 K and source-to-body voltage V(sb) ≥ 0 V conditions.
Subject: DRNTU::Engineering::Electrical and electronic engineering.
Type: Journal Article
Series/ Journal Title: IEEE transactions on electron devices
School: School of Electrical and Electronic Engineering
Rights: © 2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
Version: Published version

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