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Modeling and layout optimization of differential inductors for Silicon-based RFIC applications

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Modeling and layout optimization of differential inductors for Silicon-based RFIC applications

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dc.contributor.author Sia, Choon Beng
dc.contributor.author Ong, Beng Hwee
dc.contributor.author Lim, Wei Meng
dc.contributor.author Yeo, Kiat Seng
dc.contributor.author Alam, Tariq
dc.date.accessioned 2009-07-28T04:17:45Z
dc.date.available 2009-07-28T04:17:45Z
dc.date.copyright 2008
dc.date.issued 2009-07-28T04:17:45Z
dc.identifier.citation Sia, C. B., Ong, B. H., Lim, W. M., Yeo, K. S., & Alam, T. (2008). Modeling and layout optimization of differential inductors for Silicon-based RFIC applications. IEEE Transactions on Electron Devices, 55(4), 1058-1066.
dc.identifier.issn 0018-9383
dc.identifier.uri http://hdl.handle.net/10220/4710
dc.description.abstract A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs are found to yield good performance for inductors with small inductance values. As differential inductance or operating frequency increases, interactions between metallization resistive and substrate losses discourage the use of large widths as it consumes silicon area and degrades device performance.
dc.format.extent 9 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on electron devices
dc.rights © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits.
dc.title Modeling and layout optimization of differential inductors for Silicon-based RFIC applications
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TED.2008.917536
dc.description.version Published version

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