Scalable model of on-wafer interconnects for high-speed CMOS ICs

DSpace/Manakin Repository


Search DR-NTU

Advanced Search Subject Search


My Account

Scalable model of on-wafer interconnects for high-speed CMOS ICs

Show full item record

Title: Scalable model of on-wafer interconnects for high-speed CMOS ICs
Author: Shi, Xiaomeng; Yeo, Kiat Seng; Ma, Jianguo; Do, Manh Anh; Li, Erping
Copyright year: 2006
Abstract: This paper describes the development of an equivalent circuit model of on-wafer interconnects for high-speed CMOS integrated circuits. By strategically cascading two- blocks together, the lumped model can characterize the distributed effects. Besides, the elaborately proposed model characterizes the frequency-variant characteristics with frequency-independent components. Thus, the model can be easily plugged into commercial computer-aided design tools. By adopting a newly invented optimization algorithm, namely, particle swarm optimization (PSO), the model parameters are extracted and formulated as empirical expressions. Therein, with each set of the geometrical parameters, the interconnect behaviors can be accurately predicted. The accuracy of the model is validated by comparisons with the on-wafer measurements up to 30 GHz. Moreover, the scalability of the proposed model is also discussed.
Subject: DRNTU::Engineering::Electrical and electronic engineering.
Type: Journal Article
Series/ Journal Title: IEEE transactions on advanced packaging
School: School of Electrical and Electronic Engineering
Rights: © 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
Version: Published version

Files in this item

Files Size Format View Description
Scalable Model ... or High-Speed CMOS ICs.pdf 753.8Kb PDF View/Open Published version

DOI Query

- Get published version (via Digital Object Identifier)

This item appears in the following Collection(s)

Show full item record


Total views

All Items Views
Scalable model of on-wafer interconnects for high-speed CMOS ICs 347

Total downloads

All Bitstreams Views
Scalable Model of On-Wafer Interconnects for High-Speed CMOS ICs.pdf 438

Top country downloads

Country Code Views
United States of America 153
China 58
Germany 51
Russian Federation 27
Singapore 18

Top city downloads

city Views
Mountain View 71
Kiez 16
Singapore 14
Beijing 12
Scranton 11