| dc.contributor.author |
Shi, Xiaomeng. |
| dc.contributor.author |
Yeo, Kiat Seng. |
| dc.contributor.author |
Ma, Jianguo. |
| dc.contributor.author |
Do, Manh Anh. |
| dc.contributor.author |
Li, Erping. |
| dc.date.accessioned |
2009-07-28T07:01:55Z |
| dc.date.available |
2009-07-28T07:01:55Z |
| dc.date.copyright |
2006 |
| dc.date.issued |
2009-07-28T07:01:55Z |
| dc.identifier.citation |
Shi, X., Yeo, K. S., Ma, J. G., Do, M. A., & Li, E. (2006). Scalable model of on-wafer interconnects for high-speed CMOS ICs. IEEE Transactions on Advanced Packaging, 29(4), 770-776. |
| dc.identifier.issn |
1521-3323 |
| dc.identifier.uri |
http://hdl.handle.net/10220/4713 |
| dc.description.abstract |
This paper describes the development of an equivalent circuit model of on-wafer interconnects for high-speed CMOS integrated circuits. By strategically cascading two- blocks together, the lumped model can characterize the distributed effects. Besides, the elaborately proposed model characterizes the frequency-variant characteristics with frequency-independent components. Thus, the model can be easily plugged into commercial computer-aided design tools. By adopting a newly invented optimization algorithm, namely, particle swarm optimization (PSO), the model parameters are extracted and formulated as empirical expressions. Therein, with each set of the geometrical parameters, the interconnect behaviors can be accurately predicted. The accuracy of the model is validated by comparisons with the on-wafer measurements up to 30 GHz. Moreover, the scalability of the proposed model is also discussed. |
| dc.format.extent |
7 p. |
| dc.language.iso |
en |
| dc.relation.ispartofseries |
IEEE transactions on advanced packaging |
| dc.rights |
© 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. |
| dc.subject |
DRNTU::Engineering::Electrical and electronic engineering. |
| dc.title |
Scalable model of on-wafer interconnects for high-speed CMOS ICs. |
| dc.type |
Journal Article |
| dc.contributor.school |
School of Electrical and Electronic Engineering |
| dc.identifier.doi |
http://dx.doi.org/10.1109/TADVP.2006.884781 |
| dc.description.version |
Published version |
