| dc.contributor.author |
Yu, Xiao Peng. |
| dc.contributor.author |
Do, Manh Anh. |
| dc.contributor.author |
Lim, Wei Meng. |
| dc.contributor.author |
Yeo, Kiat Seng. |
| dc.contributor.author |
Ma, Jianguo. |
| dc.date.accessioned |
2009-07-31T06:26:26Z |
| dc.date.available |
2009-07-31T06:26:26Z |
| dc.date.copyright |
2006 |
| dc.date.issued |
2009-07-31T06:26:26Z |
| dc.identifier.citation |
Yu, X. P., Do, M. A., Lim, W. M., Yeo, K. S., & Ma, J. (2006). Design and optimization of the extended true single-phase clock-based prescaler. IEEE Transactions on Microwave Theory and Techniques, 54(11), 3828-3835. |
| dc.identifier.issn |
0018-9480 |
| dc.identifier.uri |
http://hdl.handle.net/10220/5950 |
| dc.description.abstract |
The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-µm CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications. |
| dc.format.extent |
8 p. |
| dc.language.iso |
en |
| dc.relation.ispartofseries |
IEEE transactions on microwave theory and techniques |
| dc.rights |
IEEE Transactions on Microwave Theory and Techniques © 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site. |
| dc.subject |
DRNTU::Engineering::Electrical and electronic engineering. |
| dc.title |
Design and optimization of the extended true single-phase clock-based prescaler. |
| dc.type |
Journal Article |
| dc.contributor.school |
School of Electrical and Electronic Engineering |
| dc.identifier.doi |
http://dx.doi.org/10.1109/TMTT.2006.884629 |
| dc.description.version |
Published version |
