| dc.contributor.author |
Shi, Xiaomeng. |
| dc.contributor.author |
Ma, Jianguo. |
| dc.contributor.author |
Yeo, Kiat Seng. |
| dc.contributor.author |
Do, Manh Anh. |
| dc.contributor.author |
Li, Erping. |
| dc.date.accessioned |
2009-07-31T07:22:24Z |
| dc.date.available |
2009-07-31T07:22:24Z |
| dc.date.copyright |
2005 |
| dc.date.issued |
2009-07-31T07:22:24Z |
| dc.identifier.citation |
Shi, X., Ma, J. G., Yeo, K. S., Do, M. A., & Li, E. (2005). Equivalent circuit model of on-wafer CMOS interconnects for RFICs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(9), 1060-1071. |
| dc.identifier.issn |
1063-8210 |
| dc.identifier.uri |
http://hdl.handle.net/10220/5983 |
| dc.description.abstract |
This paper investigates the properties of the on-wafer interconnects built in a 0.18-µm CMOStechnology for RF applications.
A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include the frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated. |
| dc.format.extent |
12 p. |
| dc.language.iso |
en |
| dc.relation.ispartofseries |
IEEE transactions on very large scale integration (VLSI) systems |
| dc.rights |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems © 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site. |
| dc.subject |
DRNTU::Engineering::Electrical and electronic engineering. |
| dc.title |
Equivalent circuit model of on-wafer CMOS interconnects for RFICs. |
| dc.type |
Journal Article |
| dc.contributor.school |
School of Electrical and Electronic Engineering |
| dc.identifier.doi |
http://dx.doi.org/10.1109/TVLSI.2005.857177 |
| dc.description.version |
Published version |
