Energy-efficient synchronous-logic and asynchronous-logic FFT/IFFT processors

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Energy-efficient synchronous-logic and asynchronous-logic FFT/IFFT processors

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dc.contributor.author Chong, Kwen-Siong
dc.contributor.author Gwee, Bah Hwee
dc.contributor.author Chang, Joseph Sylvester
dc.date.accessioned 2009-08-03T03:54:29Z
dc.date.available 2009-08-03T03:54:29Z
dc.date.copyright 2007
dc.date.issued 2009-08-03T03:54:29Z
dc.identifier.citation Chong, K. S., Gwee, B. H. & Chang, J. S. (2007). Energy-efficient synchronous-logic and asynchronous-logic FFT/IFFT processors. IEEE journal of solid-state circuits, 42(9), 2034-1045.
dc.identifier.issn 0018-9200
dc.identifier.uri http://hdl.handle.net/10220/6004
dc.description.abstract Two 128-point 16-bit radix-2 FFT/IFFT processors based on synchronous-logic (sync) and asynchronous-logic (async) for low voltage (1.1–1.4 V) energy-critical low-speed hearing aids are described. The two processors herein are designed with the same function and similar architecture, and the emphasis is energy efficacy. The async approach, on average, features 37% lower energy per FFT/IFFT computation than the sync approach but with 10% larger IC area penalty and an inconsequential 1.4 times worse delay; the async design can be designed to be 0.24 times faster and with largely the same energy dissipation if the matched delay elements and the latch controllers therein are better optimized. In this low-speed application, the lower energy feature of the async design is not attributed to the absence of the clock infrastructure but instead due to the adoption of established and proposed async circuit designs, resulting in reduced redundant operations and reduced spurious/glitch switching, and to the use of latches. The prototype async FFT/IFFT processor (in a 0.35- m CMOS process) can be operated at 1.0 V and dissipates 93 nJ.
dc.format.extent 12 p.
dc.language.iso en
dc.relation.ispartofseries IEEE journal of solid-state circuits
dc.rights IEEE Journal of Solid-State Circuits © 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site.
dc.subject DRNTU::Engineering::Electrical and electronic engineering
dc.title Energy-efficient synchronous-logic and asynchronous-logic FFT/IFFT processors
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/JSSC.2007.903039
dc.description.version Published version

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