A low-power 16×16-b parallel multiplier utilizing pass-transistor logic

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A low-power 16×16-b parallel multiplier utilizing pass-transistor logic

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dc.contributor.author Law, C. F.
dc.contributor.author Rofail, Samir S.
dc.contributor.author Yeo, Kiat Seng
dc.date.accessioned 2009-08-03T04:45:40Z
dc.date.available 2009-08-03T04:45:40Z
dc.date.copyright 1999
dc.date.issued 2009-08-03T04:45:40Z
dc.identifier.citation Law, C. F., Rofail, S. S., & Yeo., K. S. (1999). A low-power 16 16-b parallel multiplier utilizing pass-transistor logic. IEEE Journal of Solid-State Circuits, 34(10), 1395-1399.
dc.identifier.issn 0018-9200
dc.identifier.uri http://hdl.handle.net/10220/6009
dc.description.abstract This paper describes a low-power 16x16-b parallel very large scale integration multiplier, designed and fabricated using a 0.8- m double-metal double-poly BiCMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor (PT) logic circuits. The inherent nonfull-swing nature of PT logic circuits were taken full advantage of, without significantly compromising the speed performance of the overall circuit implementation. New circuit implementations for the partial-product generator and the partial-product addition circuitry have been proposed, simulated, and fabricated. Experimental results showed that the worst case multiplication time of the test chip is 10.4 ns at a supply voltage of 3.3 V, and the average power dissipation is 38 mW at a frequency of 10 MHz.
dc.format.extent 5 p.
dc.language.iso en
dc.relation.ispartofseries IEEE journal of solid-state circuits
dc.rights IEEE Journal of Solid-State Circuits © 1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title A low-power 16×16-b parallel multiplier utilizing pass-transistor logic
dc.type Journal Article
dc.identifier.doi http://dx.doi.org/10.1109/4.792613
dc.description.version Published version

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