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A review of 0.18-µm full adder performances for tree structured arithmetic circuits

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A review of 0.18-µm full adder performances for tree structured arithmetic circuits

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dc.contributor.author Chang, Chip Hong
dc.contributor.author Gu, Jiang Min
dc.contributor.author Zhang, Mingyan
dc.date.accessioned 2009-08-03T05:51:37Z
dc.date.available 2009-08-03T05:51:37Z
dc.date.copyright 2005
dc.date.issued 2009-08-03T05:51:37Z
dc.identifier.citation Chang, C. H., Gu, J. M., & Zhang, M. (2005). A review of 0.18-µm full adder performances for tree structured arithmetic circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(6), 686-695.
dc.identifier.issn 1063-8210
dc.identifier.uri http://hdl.handle.net/10220/6013
dc.description.abstract The general objective of our work is to investigate the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation circuits of the proposed full adder are designed with hybrid logic styles. To operate at ultra-low supply voltage, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved to overcome the switching delay problem. As full adders are frequently employed in a tree structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is introduced to evaluate the full adders in a realistic application environment. A systematic and elegant procedure to scale the transistor for minimal power-delay product is proposed. The circuits being studied are optimized for energy efficiency at 0.18-µm CMOS process technology. With the proposed simulation environment, it is shown that some survival cells in stand alone operation at low voltage may fail when cascaded in a larger circuit, either due to the lack of drivability or unsatisfactory speed of operation. The proposed hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability. The increase in the transistor count of its complementary CMOS output stage is compensated by its area efficient layout. Therefore, it remains one of the best contenders for designing large tree structured arithmetic circuits with reduced energy consumption while keeping the increase in area to a minimum.
dc.format.extent 10 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on very large scale integration (VLSI) systems
dc.rights IEEE Transactions on Very Large Scale Integration (VLSI) Systems © 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site.
dc.subject DRNTU::Engineering::Electrical and electronic engineering
dc.title A review of 0.18-µm full adder performances for tree structured arithmetic circuits
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TVLSI.2005.848806
dc.description.version Published version

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