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Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers

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Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers

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Title: Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers
Author: Goh, Wang Ling; Montgomery, J. H.; Raza, S. H.; Gamble, H. S.; Armstrong, B. M.
Copyright year: 1997
Abstract: Dielectrically isolated substrates containing buried highly conducting WSi2 layers are characterized for the first time using MOS capacitors. The active silicon layer is approximately 3 µm thick with a buried WSi2 layer 120 mm thick adjacent to the isolation layer. The buried metal forms the back contact of the capacitor and excellent MOS characteristics are observed. Minority carrier lifetimes in excess of 200 µs were measured indicating the suitability of these substrates for use in device manufacture.
Subject: DRNTU::Engineering::Electrical and electronic engineering
Type: Journal Article
Series/ Journal Title: IEEE electron device letters
School: School of Electrical and Electronic Engineering
Rights: IEEE Electron Device Letters © 1997 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site.
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