Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/91237
Title: | Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler | Authors: | Yeo, Kiat Seng Boon, Chirn Chye Lim, Wei Meng Do, Manh Anh Krishna, Manthena Vamshi |
Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits | Issue Date: | 2010 | Source: | Yeo, K. S, Boon, C. C., Lim, W. M., Do, M. A. & Krishna, M. V. (2010). Design and Analysis of Ultra low power True single phase clock CMOS 2/3 prescaler. IEEE Transactions on Circuits and Systems I: Regular Paper, 57(1), 72-82. | Series/Report no.: | IEEE transactions on circuits and systems—I | Abstract: | In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus prescaler implemented with this 2/3 prescaler using a Chartered 0.18 m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW. | URI: | https://hdl.handle.net/10356/91237 http://hdl.handle.net/10220/6213 |
ISSN: | 1549-8328 | DOI: | 10.1109/TCSI.2009.2016183 | Schools: | School of Electrical and Electronic Engineering | Rights: | © 2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. | Fulltext Permission: | open | Fulltext Availability: | With Fulltext |
Appears in Collections: | EEE Journal Articles |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
Design and Analysis of Ultra low power True single phase clock CMOS 2-3 prescaler.pdf | 1.69 MB | Adobe PDF | View/Open |
SCOPUSTM
Citations
5
72
Updated on Mar 22, 2024
Web of ScienceTM
Citations
5
56
Updated on Oct 27, 2023
Page view(s) 1
2,335
Updated on Mar 28, 2024
Download(s) 1
4,625
Updated on Mar 28, 2024
Google ScholarTM
Check
Altmetric
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.