| dc.contributor.author |
Yeo, Kiat Seng. |
| dc.contributor.author |
Boon, Chirn Chye. |
| dc.contributor.author |
Lim, Wei Meng. |
| dc.contributor.author |
Do, Manh Anh. |
| dc.contributor.author |
Krishna, Manthena Vamshi. |
| dc.date.accessioned |
2010-04-06T01:18:07Z |
| dc.date.available |
2010-04-06T01:18:07Z |
| dc.date.copyright |
2010 |
| dc.date.issued |
2010-04-06T01:18:07Z |
| dc.identifier.citation |
Yeo, K. S, Boon, C. C., Lim, W. M., Do, M. A. & Krishna, M. V. (2010). Design and Analysis of Ultra low power True single phase clock CMOS 2/3 prescaler. IEEE Transactions on Circuits and Systems I: Regular Paper, 57(1), 72-82. |
| dc.identifier.issn |
1549-8328 |
| dc.identifier.uri |
http://hdl.handle.net/10220/6213 |
| dc.description.abstract |
In this paper the power consumption and operating
frequency of true single phase clock (TSPC) and extended true
single phase clock (E-TSPC) frequency prescalers are investigated.
Based on this study a new low power and improved speed TSPC
2/3 prescaler is proposed which is silicon verified. Compared with
the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of
power consumption is achieved when compared under the same
technology at supply voltage of 1.8 V. This extremely low power
consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2
operation. A divide-by-32/33 dual modulus prescaler implemented
with this 2/3 prescaler using a Chartered 0.18 m CMOS technology
is capable of operating up to 4.5 GHz with a power consumption
of 1.4 mW. |
| dc.format.extent |
12 p. |
| dc.language.iso |
en |
| dc.relation.ispartofseries |
IEEE transactions on circuits and systems—I |
| dc.rights |
© 2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. |
| dc.subject |
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits. |
| dc.title |
Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler. |
| dc.type |
Journal Article |
| dc.contributor.school |
School of Electrical and Electronic Engineering |
| dc.identifier.doi |
http://dx.doi.org/10.1109/TCSI.2009.2016183 |
| dc.description.version |
Published version |
