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Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM

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Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM

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dc.contributor.author Do, Anh Tuan
dc.contributor.author Kong, Zhi Hui
dc.contributor.author Yeo, Kiat Seng
dc.contributor.author Low, Jeremy Yung Shern
dc.date.accessioned 2010-04-30T00:48:43Z
dc.date.available 2010-04-30T00:48:43Z
dc.date.copyright 2009
dc.date.issued 2010-04-30T00:48:43Z
dc.identifier.citation Do, A. T., Kong, Z. H., Yeo, K. S. & Low, Y. S. (2009). Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9, 1-1.
dc.identifier.issn 1063-8210
dc.identifier.uri http://hdl.handle.net/10220/6238
dc.description.abstract A new current-mode sense amplifier is presented. It extensively utilizes the cross-coupled inverters for both local and global sensing stages, hence achieving ultra low-power and ultra high-speed properties simultaneously. Its sensing delay and power consumption are almost independent of the bit- and data-line capacitances. Extensive post-layout simulations, based on an industry standard 1 V/65-nm CMOS technology, have verified that the new design outperforms other designs in comparison by at least 27% in terms of speed and 30% in terms of power consumption. Sensitivity analysis has proven that the new design offers the best reliability with the smallest standard deviation and bit-error-rate (BER). Four 32 32-bit SRAM macros have been used to validate the proposed design, in comparison with three other circuit topologies. The new design can operate at a maximum frequency of 1.25 GHz at 1 V supply voltage and a minimum supply voltage of 0.2 V. These attributes of the proposed circuit make it a wise choice for contemporary high-complexity systems where reliability and power consumption are of major concerns.
dc.format.extent 9 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on very large scale integration (VLSI) systems
dc.rights © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title Design and sensitivity analysis of a new current-mode sense amplifier for low-power SRAM
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TVLSI.2009.2033110
dc.description.version Published version

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