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Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing

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Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing

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Title: Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing
Author: Zhu, Ning; Goh, Wang Ling; Zhang, Weija; Yeo, Kiat Seng; Kong, Zhi Hui
Copyright year: 2009
Abstract: In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.
Subject: DRNTU::Engineering::Electrical and electronic engineering.
Type: Journal Article
Series/ Journal Title: IEEE transactions on very large scale integration (VLSI) systems
School: School of Electrical and Electronic Engineering
Version: Published version

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