| dc.contributor.author |
Zhu, Ning. |
| dc.contributor.author |
Goh, Wang Ling. |
| dc.contributor.author |
Zhang, Weija. |
| dc.contributor.author |
Yeo, Kiat Seng. |
| dc.contributor.author |
Kong, Zhi Hui. |
| dc.date.accessioned |
2010-04-30T06:54:26Z |
| dc.date.available |
2010-04-30T06:54:26Z |
| dc.date.copyright |
2009 |
| dc.date.issued |
2010-04-30T06:54:26Z |
| dc.identifier.citation |
Zhu, N., Goh, W. L., Zhang, W., Yeo, K. S., & Kong, Z. H. (2009). Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing. IEEE Transactions On Very Large Scale Integration (VLSI) Systems. pp, 1-5. |
| dc.identifier.issn |
1063-8210 |
| dc.identifier.uri |
http://hdl.handle.net/10220/6241 |
| dc.description.abstract |
In modern VLSI technology, the occurrence of all kinds of
errors has become inevitable. By adopting an emerging concept in VLSI
design and test, error tolerance (ET), a novel error-tolerant adder (ETA)
is proposed. The ETA is able to ease the strict restriction on accuracy, and
at the same time achieve tremendous improvements in both the power
consumption and speed performance. When compared to its conventional
counterparts, the proposed ETA is able to attain more than 65% improvement
in the Power-Delay Product (PDP). One important potential
application of the proposed ETA is in digital signal processing systems that
can tolerate certain amount of errors. |
| dc.format.extent |
5 p. |
| dc.language.iso |
en |
| dc.relation.ispartofseries |
IEEE transactions on very large scale integration (VLSI) systems |
| dc.subject |
DRNTU::Engineering::Electrical and electronic engineering. |
| dc.title |
Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing. |
| dc.type |
Journal Article |
| dc.contributor.school |
School of Electrical and Electronic Engineering |
| dc.identifier.doi |
http://dx.doi.org/10.1109/TVLSI.2009.2020591 |
| dc.description.version |
Published version |
