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Complex shaped on-wafer interconnects modeling for CMOS RFICs

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Complex shaped on-wafer interconnects modeling for CMOS RFICs

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dc.contributor.author Shi, Xiaomeng
dc.contributor.author Yeo, Kiat Seng
dc.contributor.author Ma, Jianguo
dc.contributor.author Do, Manh Anh
dc.contributor.author Li, Erping
dc.date.accessioned 2010-05-05T01:55:00Z
dc.date.available 2010-05-05T01:55:00Z
dc.date.copyright 2008
dc.date.issued 2010-05-05T01:55:00Z
dc.identifier.citation Shi, X., Yeo, K. S., Ma, J. G., Do, M. A., & Li, E. (2008). Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16(7), 922-926.
dc.identifier.issn 1063-8210
dc.identifier.uri http://hdl.handle.net/10220/6252
dc.description.abstract A model development methodology for complex shaped on-wafer interconnects is presented. The equivalent circuit of the entire interconnect is obtained by cascading basic subsegment models. The extracted parameters are formulated into empirical expressions. Thus, the proposed model can be easily incorporated with commercial electronic design automation (EDA) tools. The accuracy of the model is validated by the on-wafer measurements up to 20 GHz.
dc.format.extent 5 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on very large scale integration (VLSI) systems
dc.rights © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title Complex shaped on-wafer interconnects modeling for CMOS RFICs
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TVLSI.2008.2000445
dc.description.version Published version

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