| dc.contributor.author |
Jiang, Shan. |
| dc.contributor.author |
Do, Manh Anh. |
| dc.contributor.author |
Yeo, Kiat Seng. |
| dc.contributor.author |
Lim, Wei Meng. |
| dc.date.accessioned |
2010-05-05T03:33:29Z |
| dc.date.available |
2010-05-05T03:33:29Z |
| dc.date.copyright |
2008 |
| dc.date.issued |
2010-05-05T03:33:29Z |
| dc.identifier.citation |
Jiang, S., Do, M. A., Yeo, K. S., & Lim, W. M. (2008). An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit. IEEE Transactions on Circuits and Systems—I. 55(6), 1430-1440. |
| dc.identifier.issn |
1549-8328 |
| dc.identifier.uri |
http://hdl.handle.net/10220/6256 |
| dc.description.abstract |
This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H)circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes the operational amplifier (opamp) gain, slew rate, bandwidth, and capacitor-matching requirements in pipelined ADCs. Due to the mixed-mode S/H technique, the single-stage opamps and small capacitor sizes can be used in this pipelined ADC, leading to a high speed and low-power consumption. Fabricated in a 0.18-µm CMOS process, the 8-bit pipelined ADC consumes 22 mW with
1.8-V supply voltage. When sampling at 200 MSample/s, the
prototype ADC achieves 54-dB spurious free dynamic range and 45-dB signal-to-noise and distortion ratio. The measured integral nonlinearity and differential nonlinearity are 0.34 LSB and 0.3 LSB, respectively. |
| dc.format.extent |
11 p. |
| dc.language.iso |
en |
| dc.relation.ispartofseries |
IEEE transactions on circuits and systems—I |
| dc.rights |
© 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. |
| dc.subject |
DRNTU::Engineering::Electrical and electronic engineering. |
| dc.title |
An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit. |
| dc.type |
Journal Article |
| dc.contributor.school |
School of Electrical and Electronic Engineering |
| dc.identifier.doi |
http://dx.doi.org/10.1109/TCSI.2008.916613 |
| dc.description.version |
Published version |
