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IP watermarking using incremental technology mapping at logic synthesis level.

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IP watermarking using incremental technology mapping at logic synthesis level.

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dc.contributor.author Cui, Aijiao.
dc.contributor.author Chang, Chip Hong.
dc.contributor.author Tahar, Sofiène.
dc.date.accessioned 2010-05-05T04:27:09Z
dc.date.available 2010-05-05T04:27:09Z
dc.date.copyright 2008
dc.date.issued 2010-05-05T04:27:09Z
dc.identifier.citation Cui, A., Chang, C. H., & Tahar, S. (2008). IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27(9), 1565-1570.
dc.identifier.issn 0278-0070
dc.identifier.uri http://hdl.handle.net/10220/6259
dc.description.abstract This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. The headroom of each disjoint closed cone is evaluated based on its slack and slack sustainability. The notion of slack sustainability in conjunction with an embedding threshold enables closed cones in the critical path to be qualified as watermark hosts if their slacks can be better preserved upon remapping. The watermark is embedded by remapping only qualified disjoint closed cones randomly selected and templates constrained by the signature. This parametric formulation provides a means to capitalize on the headroom of a design to increase the signature length or strengthen the watermark resilience. With the master design, the watermarked design can be authenticated as in nonoblivious media watermarking. Experimental results show that the design can be efficiently marked by our method with low overhead.
dc.format.extent 6 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on computer-aided design of integrated circuits and systems
dc.rights © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title IP watermarking using incremental technology mapping at logic synthesis level.
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TCAD.2008.927732
dc.description.version Published version

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