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Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power

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Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power

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dc.contributor.author Yu, Hao
dc.contributor.author Shi, Yiyu
dc.contributor.author He, Lei
dc.contributor.author Karnik, Tanay
dc.date.accessioned 2010-05-05T06:17:45Z
dc.date.available 2010-05-05T06:17:45Z
dc.date.copyright 2008
dc.date.issued 2010-05-05T06:17:45Z
dc.identifier.citation Yu, H., Shi, Y., He, L., & Karnik, T. (2008). Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(12), 1609-1619.
dc.identifier.issn 1063-8210
dc.identifier.uri http://hdl.handle.net/10220/6262
dc.description.abstract The existing 3-D thermal-via allocation methods are based on the steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and efficient thermal-via allocation considering the temporally and spatially variant thermal-power. The transient temperature is calculated by macromodel with a one-time structured and parameterized model reduction, which also generates temperature sensitivity with respect to thermal-via density. The proposed thermal-via allocation minimizes the time-integral of temperature violation, and is solved by a sequential quadratic programming algorithm with use of sensitivities from the macromodel. Compared to the existing method using the steady-state thermal analysis, our method in experiments is 126x faster to obtain temperature, and reduces the number of thermal vias by 2.04x under the same temperature bound.
dc.format.extent 11 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on very large scale integration (VLSI) systems
dc.rights © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits.
dc.title Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TVLSI.2008.2001297
dc.description.version Published version
dc.identifier.rims 148333

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