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A study of on-chip stacked multi-loop spiral inductors

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A study of on-chip stacked multi-loop spiral inductors

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dc.contributor.author Yang, Kai
dc.contributor.author Yin, Wen Yan
dc.contributor.author Shi, Jinglin
dc.contributor.author Kang, Kai
dc.contributor.author Mao, Jun Fa
dc.contributor.author Zhang, Yue Ping
dc.date.accessioned 2010-05-05T06:50:42Z
dc.date.available 2010-05-05T06:50:42Z
dc.date.copyright 2008
dc.date.issued 2010-05-05T06:50:42Z
dc.identifier.citation Yang, K., Yin, W. Y., Shi, J., Kang, K., Mao, J. F., & Zhang, Y. P. (2008). Study of On-Chip Stacked Multiloop Spiral Inductors. IEEE Transactions on Electron Devices. 55(11), 3236-3245.
dc.identifier.issn 0018-9383
dc.identifier.uri http://hdl.handle.net/10220/6264
dc.description.abstract This paper proposes a new differential topology that features a stacked multiloop inductor. Comparative studies of stacked one- to four-loop spiral inductors with and without patterned ground shields (PGSs) for silicon-based radio-frequency integrated circuits (RFICs) were conducted, and lumped-element circuit models were developed for these inductors. The partialelement equivalent-circuit method that can accurately analyze mutual inductive couplings among different spirals in these multiloop geometries was employed for capturing the frequency dependent inductances and resistances of inductors at low frequencies. A good agreement between numerical results and measurements is obtained. It is demonstrated that a stacked multiloop spiral inductor with differential topology and PGS has a larger inductance and a higher Q-factor as compared with the same inductor without differential topology and PGS. This hybrid methodology could provide a promising technique for developing new silicon-based passive devices used in RFICs.
dc.format.extent 10 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on electron devices
dc.rights © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title A study of on-chip stacked multi-loop spiral inductors
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TED.2008.2004648
dc.description.version Published version

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