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K-locked-loop and its application in time mode ADC

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K-locked-loop and its application in time mode ADC

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dc.contributor.author Hor, Hon Cheong
dc.contributor.author Siek, Liter
dc.date.accessioned 2010-05-11T01:26:24Z
dc.date.available 2010-05-11T01:26:24Z
dc.date.copyright 2009
dc.date.issued 2010-05-11T01:26:24Z
dc.identifier.citation Hor, H. C., & Siek, L. (2009). Integrated Circuits, ISIC '09. In Proceedings of the 2009 12th International Symposium (pp.101-104).
dc.identifier.uri http://hdl.handle.net/10220/6283
dc.description.abstract VCO is commonly used in time mode ADC to convert analog input voltage to time/phase information, where the time/phase information is subsequently converted to digital code using time-to-digital converter. Although high speed high resolution time-to-digital converters are currently available, the inherent nonlinear property of VCO however has become the bottle neck for time mode ADC. In this paper, a new concept named K-locked-loop is proposed to solve the nonlinearity issue of VCO within a time mode ADC. A 9-bit, 0.5MS/s time mode ADC has been modeled using SIMULINK tool in Matlab. Some of the circuits are simulated using Spectre simulator tool in Cadence using the 0.18μm CSM process, and the simulation result is back annotated to SIMULINK model to make the behavioral modeling more comprehensive and accurate.
dc.format.extent 4 p.
dc.language.iso en
dc.rights © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title K-locked-loop and its application in time mode ADC
dc.type Conference Paper
dc.contributor.conference IEEE International Symposium on Integrated Circuits (12th : 2009 : Singapore)
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.openurl http://www.isic2009.org/
dc.identifier.doi http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403964
dc.description.version Published version

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