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3D circuit model for 3D IC reliability study

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3D circuit model for 3D IC reliability study

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dc.contributor.author Tan, Cher Ming
dc.contributor.author He, Feifei
dc.date.accessioned 2010-06-04T08:14:27Z
dc.date.available 2010-06-04T08:14:27Z
dc.date.copyright 2009
dc.date.issued 2010-06-04T08:14:27Z
dc.identifier.citation Tan, C. M., & He, F. (2009). 3D circuit model for 3D IC reliability study. International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems(10th:2009:Delft, The Netherlands)
dc.identifier.uri http://hdl.handle.net/10220/6292
dc.description.abstract 3D integrated circuit technology is an emerging technology for the near future, and has received tremendous attention in the semiconductor community. With the 3D integrated circuit, the temperature and thermo-mechanical stress in the various parts of the IC are highly dependent on the surrounding materials and their materials properties, including their thermal conductivities, thermal expansivities, Young modulus, poisson ratio etc. Also, the architectural of the 3D IC will also affect the current density, temperature and thermomechanical stress distributions in the IC. In view of the above-mentioned, the electricalthermal- mechanical modeling of integrated circuit can no longer be done with a simple 2D model. The distributions of the current density, temperature and stress are important in determining the reliability of an IC. In this work we demonstrate a method of converting 2D circuit layo~t into a 3D model. Simulations under real circuit operating condition are carried out using both Cadence (a circuit simulator) and ANSYS (finite element tool). Limiting our study to the electromigration failure, we compute the current density, temperature and stress distributions of the interconnect layers by considering the heat transfer and Joule heating, and the "weak spot" for electromigration is identified. Layout design can be modified based on the simulation results so as to enhance the 3D circuit interconnect reliability.
dc.format.extent 7 p.
dc.language.iso en
dc.rights © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title 3D circuit model for 3D IC reliability study
dc.type Conference Paper
dc.contributor.conference IEEE International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems (10th : 2009 : Delft, The Netherlands)
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/ESIME.2009.4938513
dc.description.version Published version

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