| dc.contributor.author |
Phyu, Myint Wai. |
| dc.contributor.author |
Fu, Kang Kang. |
| dc.contributor.author |
Goh, Wang Ling. |
| dc.contributor.author |
Yeo, Kiat Seng. |
| dc.date.accessioned |
2010-08-19T00:45:47Z |
| dc.date.available |
2010-08-19T00:45:47Z |
| dc.date.copyright |
2009 |
| dc.date.issued |
2010-08-19T00:45:47Z |
| dc.identifier.citation |
Phyu, M. W., Fu, K. K., Goh, W. L., & Yeo, K. S. (2009). Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1-9. |
| dc.identifier.issn |
1063-8210 |
| dc.identifier.uri |
http://hdl.handle.net/10220/6319 |
| dc.description.abstract |
A novel explicit-pulsed dual-edge triggered sense-amplifier
flip-flop (DET-SAFF) for low-power and high-performance
applications is presented in this paper. By incorporating the
dual-edge triggering mechanism in the new fast latch and employing
conditional precharging, the DET-SAFF is able to achieve
low-power consumption that has small delay. To further reduce
the power consumption at low switching activities, a clock-gated
sense-amplifier (CG-SAFF) is engaged. Extensive post-layout
simulations proved that the proposed DET-SAFF exhibits both
the low-power and high-speed properties, with delay and power
reduction of up to 43.3% and 33.5% of those of the prior art,
respectively. When the switching activity is less than 0.5, the proposed
CG-SAFF demonstrates its superiority in terms of power
reduction. During zero input switching activity, CG-SAFF can
realize up to 86% in power saving. Lastly, a modification to the
proposed circuit has led to an improved common-mode rejection
ratio (CMRR) DET-SAFF. |
| dc.format.extent |
9 p. |
| dc.language.iso |
en |
| dc.relation.ispartofseries |
IEEE transactions on very large scale integration (VLSI) systems |
| dc.rights |
© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. |
| dc.subject |
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits. |
| dc.title |
Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops. |
| dc.type |
Journal Article |
| dc.contributor.school |
School of Electrical and Electronic Engineering |
| dc.identifier.doi |
http://dx.doi.org/10.1109/TVLSI.2009.2029116 |
| dc.description.version |
Published version |
