Intellectual property authentication by watermarking scan chain in design-for-testability flow.

Abstract

This paper proposes an intellectual property (IP)

protection scheme at the Design-for-Testability (DfT) stage of

VLSI design flow. Additional constraints generated by the

owner’s digital signature have been imposed on the NP-hard

problem of ordering the scan cells to achieve a watermarked

solution which minimizes the penalty on power and cost of

testing. As only the order of the scan cells is varied, the number

of test vectors for the desired fault coverage is not affected. The

advantage of this scheme is the ownership legitimacy can be

publicly authenticated on-site by IP buyers after the chip has

been packaged by loading a specific verification code into the

scan chain. We propose to integrate the scan chain

watermarking with dynamic watermarking of the IP core to

make the design hard-to-attack while the ownership is easy-totrace.

The proposed scheme is applied to an optimization

instance of scan cell ordering targeting at test power reduction.

The results on several MCNC benchmarks show that the

watermarking scheme has a very low probability of solution

coincidence and hence provides strong proof of authorship.