Wideband passive multiport model order reduction and realization of RLCM circuits.

Abstract

This paper presents a novel compact passive

modeling technique for high-performance RF passive and

interconnect circuits modeled as high-order resistor–inductor–

capacitor–mutual inductance circuits. The new method is based

on a recently proposed general s-domain hierarchical modeling

and analysis method and vector potential equivalent circuit model

for self and mutual inductances. Theoretically, this paper shows

that s-domain hierarchical reduction is equivalent to implicit

moment matching at around s = 0 and that the existing hierarchical

reduction method by one-point expansion is numerically

stable for general tree-structured circuits. It is also shown that

hierarchical reduction preserves the reciprocity of passive circuit

matrices. Practically, a hierarchical multipoint reduction scheme

to obtain accurate-order reduced admittance matrices of general

passive circuits is proposed. A novel explicit waveform-matching

algorithm is proposed for searching dominant poles and residues

from different expansion points based on the unique hierarchical

reduction framework. To enforce passivity, state-space-based

optimization is applied to the model order reduced admittance

matrix. Then, a general multiport network realization method

to realize the passivity-enforced reduced admittance based on

the relaxed one-port network synthesis technique using Foster’s

canonical form is proposed. The resulting modeling algorithm can

generate the multiport passive SPICE-compatible model for any

linear passive network with easily controlled model accuracy and

complexity. Experimental results on an RF spiral inductor and

a number of high-speed transmission line circuits are presented.

In comparison with other approaches, the proposed reduction is

as accurate as passive reduced-order interconnect macromodeling

algorithm in the high-frequency domain due to the enhanced

multipoint expansion, but leads to smaller realized circuit models.

In addition, under the same reduction ratio, realized models by

the new method have less error compared with reduced circuits by

time-constant-based reduction techniques in time domain.