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Statistical modeling of via redundancy effects on interconnect reliability

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Statistical modeling of via redundancy effects on interconnect reliability

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dc.contributor.author Raghavan, Nagarajan
dc.contributor.author Tan, Cher Ming
dc.date.accessioned 2010-08-23T06:21:03Z
dc.date.available 2010-08-23T06:21:03Z
dc.date.copyright 2008
dc.date.issued 2010-08-23T06:21:03Z
dc.identifier.citation Raghavan, N., & Tan, C. M. (2008). Statistical modeling of via redundancy effects on interconnect reliability. International Symposium on the Physical and Failure Analysis of Integrated Circuits (pp.1-5) Singapore.
dc.identifier.uri http://hdl.handle.net/10220/6345
dc.description.abstract Electromigration is an important failure mechanism in the nano-interconnects of modern IC technology. Various approaches have been investigated to prolong the lifetime of an interconnect. One such approach is to have an in-built redundancy in the via structures of the interconnect. The presence of redundant via in a parallel topology helps improve the overall reliability of the via structure. Although reliability improvement due to via redundancy is qualitatively understood, it is necessary to quantify the improvement in reliability through statistical models so that the improvement in lifetime as a result of redundancy can be quantified. A statistical model that incorporates the effects of redundancy is developed in this study and it is used to estimate the reliability of redundant via structures. The Cumulative Damage Model (CDM) is used in conjunction with the Maximum Likelihood Estimate (MLE) method to assess the reliability of load sharing via redundant structures in this study.
dc.format.extent 5 p.
dc.language.iso en
dc.rights © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits.
dc.title Statistical modeling of via redundancy effects on interconnect reliability
dc.type Conference Paper
dc.contributor.conference IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (15th : 2008 : Singapore)
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/IPFA.2008.4588156
dc.description.version Published version
dc.contributor.organization Singapore-MIT Alliance (SMA)

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