mirage

An enhanced low-power high-speed adder for error-tolerant application

DSpace/Manakin Repository

 

Search DR-NTU


Advanced Search Subject Search

Browse

My Account

An enhanced low-power high-speed adder for error-tolerant application

Show simple item record

dc.contributor.author Zhu, Ning
dc.contributor.author Goh, Wang Ling
dc.contributor.author Yeo, Kiat Seng
dc.date.accessioned 2010-08-25T00:44:13Z
dc.date.available 2010-08-25T00:44:13Z
dc.date.copyright 2009
dc.date.issued 2010-08-25T00:44:13Z
dc.identifier.citation Zhu, N., Goh, W. L., & Yeo, K. S. (2009). An enhanced low-power high-speed adder for error-tolerant application. Proceedings of the 12th International Symposium on Integrated Circuits, (pp.69-72) Singapore.
dc.identifier.uri http://hdl.handle.net/10220/6350
dc.description.abstract The occurrence of errors are inevitable in modern VLSI technology and to overcome all possible errors is an expensive task. It not only consumes a lot of power but degrades the speed performance. By adopting an emerging concept in VLSI design and test—Error- Tolerance (ET), we managed to develop a novel Error-Tolerant Adder which we named the Type II (ETAII). The circuit to some extent is able to ease the strict restriction on accuracy to achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETAII is able to achieve more than 60% improvement in the Power- Delay Product (PDP). The proposed ETAII is an enhancement of our earlier design, the ETAI, which has problem adding small number inputs.
dc.format.extent 4 p.
dc.language.iso en
dc.rights © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title An enhanced low-power high-speed adder for error-tolerant application
dc.type Conference Paper
dc.contributor.conference IEEE International Symposium on Integrated Circuits (12th : 2009 : Singapore)
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.openurl http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403865
dc.description.version Published version

Files in this item

Files Size Format View
An Enhanced Low ... r-Tolerant Application.pdf 391.0Kb PDF View/Open

This item appears in the following Collection(s)

Show simple item record

Statistics

Total views

All Items Views
An enhanced low-power high-speed adder for error-tolerant application 594

Total downloads

All Bitstreams Views
An Enhanced Low-Power High-Speed Adder For Error-Tolerant Application.pdf 682

Top country downloads

Country Code Views
India 197
United States of America 174
China 78
Thailand 25
Singapore 17

Top city downloads

city Views
Mountain View 87
Beijing 53
Hyderabad 45
Madras 26
New Delhi 25

Downloads / month

  2014-08 2014-09 2014-10 total
An Enhanced Low-Power High-Speed Adder For Error-Tolerant Application.pdf 0 0 6 6