| dc.contributor.author |
Hosseini, S. M. Ehsan. |
| dc.contributor.author |
Chan, Kheong Sann. |
| dc.contributor.author |
Goh, Wang Ling. |
| dc.date.accessioned |
2010-08-31T01:35:12Z |
| dc.date.available |
2010-08-31T01:35:12Z |
| dc.date.copyright |
2008 |
| dc.date.issued |
2010-08-31T01:35:12Z |
| dc.identifier.citation |
Hosseini, S. M. E., Chan, K. S., & Goh, W. L. (2008). A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes. 2nd International Conference on Signals, Circuits and Systems: Hammamet,Tunisia, (pp.1-6). |
| dc.identifier.uri |
http://hdl.handle.net/10220/6373 |
| dc.description.abstract |
This paper describes the implementation of a general
and embedded decoder for the evaluation of unstructured
low-density parity-check (LDPC) codes over additive-white Gaussian
noise (AWGN) channels. The decoder, which has a serial architecture
and moderate throughput, is a peripheral connected to
the embedded PowerPC processor of a Xilinx Virtex-II Pro FPGA
and is managed by the processor. This method of Hardware/
Software implementation provides the maximum flexibility for
the development and rapid prototyping of the hardware-based
simulator system. The decoding algorithm proposed in this paper
belongs to the class of min-sum with correction factor in which
the correction factor updates with the log-likelihood ratio (LLR)
values. |
| dc.format.extent |
6 p. |
| dc.language.iso |
en |
| dc.rights |
© 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. |
| dc.subject |
DRNTU::Engineering::Electrical and electronic engineering::Electronic systems. |
| dc.title |
A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes. |
| dc.type |
Conference Paper |
| dc.contributor.conference |
IEEE International Conference on Signals, Circuits and Systems (2nd:2008:Hammamet, Tunisia) |
| dc.contributor.school |
School of Electrical and Electronic Engineering |
| dc.identifier.doi |
http://dx.doi.org/10.1109/ICSCS.2008.4746952 |
| dc.description.version |
Published version |
| dc.contributor.organization |
Data Storage Institute, A*STAR |
