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High-speed signal termination analysis using a co-simulation approach

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High-speed signal termination analysis using a co-simulation approach

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dc.contributor.author Chang, Richard Weng Yew
dc.contributor.author See, Kye Yak
dc.contributor.author Soh, Wei-Shan
dc.contributor.author Oswal, Manish
dc.contributor.author Wang, Lin Biao
dc.date.accessioned 2010-08-31T02:47:18Z
dc.date.available 2010-08-31T02:47:18Z
dc.date.copyright 2009
dc.date.issued 2010-08-31T02:47:18Z
dc.identifier.citation Chang, R. W. Y., See, K. Y., Soh, W. S., Oswal, M., & Wang, L. B. (2009). High-speed signal termination analysis using a co-simulation approach. In proceedings of the 12th International Symposium on Integrated Circuits: Singapore, (pp.623-626).
dc.identifier.uri http://hdl.handle.net/10220/6375
dc.description.abstract Matched terminations of high-speed digital buses have long been the focus of high-speed board design. With increasing edge rates, proper bus termination has become even more crucial in today’s high-speed PCB interconnect design. Using a co-simulation approach, the 3D electromagnetic (EM) effects of high-speed interconnects and the circuit behavioral IBIS models of active devices are combined to investigate highspeed clock termination designs. Such an approach allows the high-frequency effects to be taken into account and therefore yields good accuracy for realistic high-speed board. A practical example is demonstrated based on the co-simulation approach.
dc.format.extent 4 p.
dc.language.iso en
dc.rights © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing.
dc.title High-speed signal termination analysis using a co-simulation approach
dc.type Conference Paper
dc.contributor.conference IEEE International Symposium on Integrated Circuits (12th : 2009 : Singapore)
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.openurl http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403694
dc.description.version Published version
dc.contributor.organization Guided Systems Division, DSO National Laboratories

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