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An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator.

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An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator.

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dc.contributor.author Chan, Pak Kwong.
dc.contributor.author Susanti, Yulia.
dc.contributor.author Ong, Vincent K. S.
dc.date.accessioned 2010-08-31T03:23:17Z
dc.date.available 2010-08-31T03:23:17Z
dc.date.copyright 2008
dc.date.issued 2010-08-31T03:23:17Z
dc.identifier.citation Chan, P. K., Susanti, Y., & Ong, V. K. S. (2009). An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator. In proceedings of the 9th IEEE Asia Pacific Conference on Circuits and Systems: Macau, (pp.284-287).
dc.identifier.uri http://hdl.handle.net/10220/6377
dc.description.abstract This paper presents a new offset-biased autozero comparator for the design of an ultra low-power charge redistribution Successive Approximation Analogto- Digital Converter (SA-ADC) dedicated to biomedical applications. The circuits are realized in CSM 0.18μm CMOS technology. The simulated results have shown that the power consumption of the 10-bit ADC is only 6.2μW at a single supply of 1.8V whilst sampling at a frequency of 64kHz, with conversion time of 187.5μs. The energy per quantization level is less than 0.1pJ/level.
dc.format.extent 4 p.
dc.language.iso en
dc.rights © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits.
dc.title An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator.
dc.type Conference Paper
dc.contributor.conference IEEE Asia Pacific Conference on Circuits and Systems (2008 : Macau)
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/APCCAS.2008.4746015
dc.description.version Published version

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