| dc.contributor.author |
Loy, Liang Yu. |
| dc.contributor.author |
Zhang, Weijia. |
| dc.contributor.author |
Kong, Zhi Hui. |
| dc.contributor.author |
Goh, Wang Ling. |
| dc.contributor.author |
Yeo, Kiat Seng. |
| dc.date.accessioned |
2010-08-31T03:37:05Z |
| dc.date.available |
2010-08-31T03:37:05Z |
| dc.date.copyright |
2008 |
| dc.date.issued |
2010-08-31T03:37:05Z |
| dc.identifier.citation |
Loy, L. Y., Zhang, W., Kong, Z. H., Goh, W. L., & Yeo, K. S. (2008). Body-bootstrapped-buffer circuit for CMOS static power reduction. In proceedings of the 9th IEEE Asia Pacific Conference on Circuits and Systems: Macau, China, (pp.842-845). |
| dc.identifier.uri |
http://hdl.handle.net/10220/6378 |
| dc.description.abstract |
In this paper, we present a new CMOS circuit design for increasing the threshold voltages (VT) of MOSFETS to reduce power consumption. Using a single voltage source VDD, the proposed circuit generates both the high positive and negative voltages, which are connected to the body nodes of MOSFETs to increase the reverse-bias voltage between the source and body in order to raise VT. Consequentially, static power consumption is reduced. The circuit is integrated into a 256-bit Ripple Carry Adder and a 32-bit Braun multiplier. Simulation results based on Chartered Semiconductor Manufacturing Private Limited’s (CHRT) 0.25-μm, 0.18-μm and Berkeley Predictive Technology Model’s (BPTM) 90-nm processes showed good trade-offs between power savings and delay. |
| dc.format.extent |
4 p. |
| dc.language.iso |
en |
| dc.rights |
© 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. |
| dc.subject |
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits. |
| dc.title |
Body-bootstrapped-buffer circuit for CMOS static power reduction. |
| dc.type |
Conference Paper |
| dc.contributor.conference |
IEEE Asia Pacific Conference on Circuits and Systems (2008:Macau) |
| dc.contributor.school |
School of Electrical and Electronic Engineering |
| dc.identifier.doi |
http://dx.doi.org/10.1109/APCCAS.2008.4746154 |
| dc.description.version |
Published version |
