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Impacts of bends and ground return vias on interconnects for high speed GHz designs

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Impacts of bends and ground return vias on interconnects for high speed GHz designs

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dc.contributor.author Chang, Richard Weng Yew
dc.contributor.author See, Kye Yak
dc.contributor.author Tan, Yang Long
dc.date.accessioned 2010-09-02T03:59:54Z
dc.date.available 2010-09-02T03:59:54Z
dc.date.copyright 2008
dc.date.issued 2010-09-02T03:59:54Z
dc.identifier.citation Chang, R. W. Y., See, K. Y., & Tan, Y. L. (2008). Impacts of bends and ground return vias on interconnects for high speed GHz designs. In proceedings of the Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility: Singapore, (pp.502-505).
dc.identifier.uri http://hdl.handle.net/10220/6386
dc.description.abstract In the past only critical clock circuits are running at high speed but this is no longer true in today high-speed digital design world. Most of the digital traces on board are running at speed in excess of 200 MHz and drivers output with rise time less than 1 ns. Due to constraints of board size and highly complex designs, trace bends and inter-layer transitions through vias are unavoidable. This paper carries out a comprehensive study on the impacts of bends and ground return vias optimisation on signal integrity performance using a full-wave electromagnetic simulator. (CST Microwave Studio). This study will provide high-speed digital designers an in-depth assessment of these effects in high-speed GHz applications so that some design guides to avoid these effects can be established.
dc.format.extent 4 p.
dc.language.iso en
dc.rights © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging.
dc.title Impacts of bends and ground return vias on interconnects for high speed GHz designs
dc.type Conference Paper
dc.contributor.conference Asia-Pacific Symposium on Electromagnetic Compatibility and International Zurich Symposium on Electromagnetic Compatibility (19th : 2008 : Singapore)
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/APEMC.2008.4559922
dc.description.version Published version
dc.contributor.organization Guided Systems Division, DSO National Laboratories

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