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Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides

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Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides

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dc.contributor.author Chen, Q.
dc.contributor.author Zhao, P.
dc.contributor.author Tseng, Ampere A.
dc.contributor.author Ng, Chi Yung
dc.contributor.author Chen, Tupei
dc.contributor.author Ding, Liang
dc.contributor.author Liu, Yang
dc.contributor.author Fung, Stevenson Hon Yuen
dc.date.accessioned 2010-09-06T02:52:04Z
dc.date.available 2010-09-06T02:52:04Z
dc.date.copyright 2006
dc.date.issued 2010-09-06T02:52:04Z
dc.identifier.citation Chen, Q., Zhao, P., Tseng, A. A., Ng, C. Y., Chen T. P., Ding, L., et al. (2006). Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides. IEEE Transactions on Electron Devices, 53(5), 1280-1282.
dc.identifier.issn 0018-9383
dc.identifier.uri http://hdl.handle.net/10220/6405
dc.description.abstract Effect of the trapped Si ions in a 30-nm gate oxide implanted with Si+ at a very low energy (1.3 keV) on the flatband voltage after various thermal annealing has been examined. For the annealing at 700°C for 20 min, although only 0.1 per cent of the implanted Si ions remained, it can cause a flatband voltage shift of -21.3 V, and the flatband voltage shift reduces with time under a negative gate voltage showing neutralization of the trapped ions by the injected electrons from the gate. However, the annealing at 900°C for 20 min has reduced the number of the remaining ions to the lowest limit corresponding to a flatband voltage shift of -0.1 V, and the application of the negative voltage does not change the flatband voltage. A higher annealing temperature or a longer annealing time does not show further improvement, suggesting that the annealing at 900°C for 20 min is sufficient for eliminating the effect of the trapped ions.
dc.format.extent 3 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on electron devices
dc.rights © 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
dc.subject DRNTU::Engineering::Electrical and electronic engineering::Electronic apparatus and materials
dc.title Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TED.2006.871841
dc.description.version Published version

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