| dc.contributor.author |
Cho, Uk Rae. |
| dc.contributor.author |
Kim, Tae Hyoung. |
| dc.contributor.author |
Yoon, Yong Jin. |
| dc.contributor.author |
Lee, Jong Cheol. |
| dc.contributor.author |
Bae, Dae Gi. |
| dc.contributor.author |
Kim, Nam Seog. |
| dc.contributor.author |
Kim, Kang Young. |
| dc.contributor.author |
Son, Young Jae. |
| dc.contributor.author |
Yang, Jeong Suk. |
| dc.contributor.author |
Sohn, Kwon Il. |
| dc.contributor.author |
Kim, Sung Tae. |
| dc.contributor.author |
Lee, In Yeol. |
| dc.contributor.author |
Lee, Kwang Jin. |
| dc.contributor.author |
Kang, Tae Gyoung. |
| dc.contributor.author |
Kim, Su Chul. |
| dc.contributor.author |
Ahn, Kee Sik. |
| dc.contributor.author |
Byun, Hyun Geun. |
| dc.date.accessioned |
2010-09-08T03:55:26Z |
| dc.date.available |
2010-09-08T03:55:26Z |
| dc.date.copyright |
2003 |
| dc.date.issued |
2010-09-08T03:55:26Z |
| dc.identifier.citation |
Cho, U. R., Kim, T. H., Yoon, Y. J., Lee, J. C., Bae, D. G., Kim, N. S., et al. (2003). A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. IEEE Journal of Solid State Circuits, 38(11), 1943-1951. |
| dc.identifier.issn |
0018-9200 |
| dc.identifier.uri |
http://hdl.handle.net/10220/6438 |
| dc.description.abstract |
A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM
achieves a data rate of 1.5 Gb/s using dynamic self-resetting
circuits [5]. Single-ended main data lines halve the data line
precharging power dissipation and the number of data lines.
Clocks phase shifted by 0 , 90 , and 270 are generated through
the proposed clock adjustment circuits. The proposed clock
adjustment circuits make input data sampled with optimized
setup/hold window. On-chip input termination with the linearity
error of 4.1% is developed to improve signal integrity at higher
data rates. A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is fabricated in
a 0.10- m CMOS process with five metals. The cell size and the
chip size are 0.845 m2 and 151.1 mm2, respectively. |
| dc.format.extent |
9 p. |
| dc.language.iso |
en |
| dc.relation.ispartofseries |
IEEE journal of solid state circuits |
| dc.rights |
© 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. |
| dc.subject |
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits. |
| dc.title |
A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. |
| dc.type |
Journal Article |
| dc.contributor.school |
School of Electrical and Electronic Engineering |
| dc.identifier.doi |
http://dx.doi.org/10.1109/JSSC.2003.818137 |
| dc.description.version |
Published version |
