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Scalable and modular memory-based systolic architectures for discrete Hartley transform

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Scalable and modular memory-based systolic architectures for discrete Hartley transform

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dc.contributor.author Meher, Pramod Kumar
dc.contributor.author Srikanthan, Thambipillai
dc.contributor.author Patra, Jagdish Chandra
dc.date.accessioned 2011-09-21T06:41:59Z
dc.date.available 2011-09-21T06:41:59Z
dc.date.copyright 2006
dc.date.issued 2011-09-21
dc.identifier.citation Meher, P. K., Srikanthan, T., & Patra, J. C. (2006). Scalable and modular memory-based systolic architectures for discrete Hartley transform. IEEE Transactions on Circuits and Systems I: Regular Papers, 53(5), 1065-1077.
dc.identifier.issn 1549-8328
dc.identifier.uri http://hdl.handle.net/10220/7091
dc.description.abstract In this paper, we present a design framework for scalable memory-based implementation of the discrete Hartley transform (DHT) using simple and efficient systolic and systolic-like structures for short and prime transform lengths, as well as, for lengths 4 and 8. We have used the proposed short-length structures to construct highly modular architectures for higher transform lengths by a new prime-factor implementation approach. The structures proposed for the prime-factor DHT, interestingly, do not involve any transposition hardware/time. Besides, it is shown here that an N-point DHT can be computed efficiently from two (N/2)-point DHTs of its even- and odd-indexed input subsequences in a recursive manner using a ROM-based multiplication stage. Apart from flexibility of implementation, the proposed structures offer significantly lower area-time complexity compared with the existing structures. The proposed schemes of computation of the DHT can conveniently be scaled not only for higher transform lengths but also according to the hardware constraint or the throughput requirement of the application.
dc.format.extent 13 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on circuits and systems I: regular papers
dc.rights © 2006 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [DOI: http://dx.doi.org/10.1109/TCSI.2006.870225].
dc.subject DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures.
dc.title Scalable and modular memory-based systolic architectures for discrete Hartley transform
dc.type Journal Article
dc.contributor.school School of Computer Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TCSI.2006.870225
dc.description.version Accepted version
dc.identifier.rims 125993

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