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High-throughput memory-based architecture for DHT using a new convolutional formulation

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High-throughput memory-based architecture for DHT using a new convolutional formulation

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dc.contributor.author Meher, Pramod Kumar
dc.contributor.author Patra, Jagdish Chandra
dc.contributor.author Swamy, M. N. S.
dc.date.accessioned 2011-09-22T03:31:18Z
dc.date.available 2011-09-22T03:31:18Z
dc.date.copyright 2007
dc.date.issued 2011-09-22
dc.identifier.citation Meher, P. K., Patra, J. C., & Swamy, M. N. S. (2007). High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation. IEEE Transactions on Circuits and Systems II: Express Briefs, 54(7), 606-610.
dc.identifier.issn 1549-7747
dc.identifier.uri http://hdl.handle.net/10220/7103
dc.description.abstract A new formulation is presented for the computation of an -point discrete Hartley transform (DHT) from two pairs of [(N/2-1)/2]-point cyclic convolutions, and further used to obtain modular structures consisting of simple and regular memory-based systolic arrays for concurrent pipelined realization of the DHT. The proposed structures for direct-memory-based implementation is found to involve nearly the same hardware complexity as those of the existing structures, but offers two to four times more throughput and two to four times less latency compared with others. The distributed-arithmetic (DA)-based implementation is also found to offer very less memory-complexity and considerably low area-delay complexity compared with the existing DA-based structures.
dc.format.extent 5 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on circuits and Systems II: express briefs
dc.rights © 2007 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [DOI: http://dx.doi.org/10.1109/TCSII.2007.894407].
dc.subject DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures.
dc.title High-throughput memory-based architecture for DHT using a new convolutional formulation
dc.type Journal Article
dc.contributor.school School of Computer Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TCSII.2007.894407
dc.description.version Accepted version
dc.identifier.rims 119086

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