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Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform

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Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform

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dc.contributor.author Meher, Pramod Kumar
dc.contributor.author Mohanty, Basant Kumar
dc.contributor.author Patra, Jagdish Chandra
dc.date.accessioned 2011-09-22T03:57:37Z
dc.date.available 2011-09-22T03:57:37Z
dc.date.copyright 2008
dc.date.issued 2011-09-22
dc.identifier.citation Meher, P. K., Mohanty, B. K., & Patra, J. C. (2008). Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform. IEEE Transactions on Circuits and Systems II: Express Briefs, 55(2), 151-155.
dc.identifier.issn 1549-7747
dc.identifier.uri http://hdl.handle.net/10220/7104
dc.description.abstract A systolic-like modular architecture is presented for hardware-efficient implementation of two-dimensional (2-D) discrete wavelet transform (DWT). The overall computation is decomposed into two distinct stages; where column processing is performed in stage-1, while row processing is performed in stage-2. Using a new data-access scheme and a novel folding technique, the computation of both the stages are performed concurrently for transposition-free implementation of 2-D DWT. The proposed design can offer nearly the same throughput rate, and requires the same or less the number of adders and multipliers as the best of the existing structures. The storage space is found to occupy most of the area in the existing 2-D DWT structures but the proposed structure does not require any on-chip or off-chip storage of input samples or storage/transposition of intermediate output. The proposed one, therefore, involves considerably less hardware complexity compared with the existing structures. Apart from that, it has less duration of cycle period in comparison to the existing structures, and has a latency of cycles while all the existing structures have latency of cycles, the filter order being small compared to the input size.
dc.format.extent 5 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on circuits and systems II: express briefs
dc.rights © 2007 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [DOI: http://dx.doi.org/10.1109/TCSII.2007.911801].
dc.subject DRNTU::Engineering::Computer science and engineering::Hardware::Integrated circuits.
dc.title Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform
dc.type Journal Article
dc.contributor.school School of Computer Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TCSII.2007.911801
dc.description.version Accepted version
dc.identifier.rims 129280

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