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Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes

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Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes

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Title: Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes
Author: Lee, Chiou Yng; Meher, Pramod Kumar; Patra, Jagdish Chandra
Copyright year: 2010
Abstract: New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2^m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.
Subject: DRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks.
Type: Journal Article
Series/ Journal Title: IEEE transactions on very large scale integration (VLSI) systems
School: School of Computer Engineering
Rights: © 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [DOI: http://dx.doi.org/10.1109/TVLSI.2009.2020593].
Version: Accepted version

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