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Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes

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Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes

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dc.contributor.author Lee, Chiou Yng
dc.contributor.author Meher, Pramod Kumar
dc.contributor.author Patra, Jagdish Chandra
dc.date.accessioned 2011-09-29T06:13:25Z
dc.date.available 2011-09-29T06:13:25Z
dc.date.copyright 2010
dc.date.issued 2011-09-29
dc.identifier.citation Lee, C. Y., Meher, P. K., & Patra, J. C. (2010). Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF (2^m) Using Multiple Parity Prediction Schemes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(8), 1234-1238.
dc.identifier.issn 1063-8210
dc.identifier.uri http://hdl.handle.net/10220/7120
dc.description.abstract New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2^m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.
dc.format.extent 5 p.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on very large scale integration (VLSI) systems
dc.rights © 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [DOI: http://dx.doi.org/10.1109/TVLSI.2009.2020593].
dc.subject DRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks.
dc.title Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes
dc.type Journal Article
dc.contributor.school School of Computer Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TVLSI.2009.2020593
dc.description.version Accepted version
dc.identifier.rims 141722

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