3D current path in stacked devices : metrics and challenges.

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3D current path in stacked devices : metrics and challenges.

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dc.contributor.author Kor, H. B.
dc.contributor.author Infante, F.
dc.contributor.author Perdu, P.
dc.contributor.author Gan, C. L.
dc.contributor.author Lewis, D.
dc.date.accessioned 2011-10-12T08:17:31Z
dc.date.available 2011-10-12T08:17:31Z
dc.date.copyright 2011
dc.date.issued 2011-10-12
dc.identifier.citation Kor, H. B., Infante, F., Perdu, P., Gan, C. L., & Lewis, D. (2011). 3D current path in stacked devices: Metrics and challenges. Paper presented at the Physical and Failure Analysis of Integrated Circuits (IPFA).
dc.identifier.uri http://hdl.handle.net/10220/7250
dc.description.abstract Although magnetic current imaging (MCI) is useful in fault isolation of devices with 2D current distributions, MCI alone cannot give the exact information of current paths in complex 3D stacked devices. Previous work has demonstrated the ability of a simulation approach to find a short circuit in 3D geometry. This approach has been challenged in the case of dense and complex 3D current paths. In this paper, the aim is to demonstrate how we can overcome this issue by using a new simulation approach instead of the previous segment by segment approach. The new approach has been validated on a complex chip with daisy chains vertically connected by vias. From the study of the simulation of three hypothesized current paths of various current lines of interest, excluding and including the interactions with neighbouring current lines (both locally and globally), it was found that interactions of a current line with its global neighbours have very important effects, compared to no interactions or only interactions with local neighbours. By simulating all the currents, it was possible to minimize the error given by the presence of several current lines in a small volume.
dc.format.extent 6 p.
dc.language.iso en
dc.rights © 2011 IEEE. This is the author created version of a work that has been peer reviewed and accepted for publication by IEEE.  It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document.  The published version is available at: http://dx.doi.org/10.1109/IPFA.2011.5992789 .
dc.subject DRNTU::Engineering::Materials::Microelectronics and semiconductor materials.
dc.title 3D current path in stacked devices : metrics and challenges.
dc.type Conference Paper
dc.contributor.conference International Symposium on the Physical and Failure Analysis of Integrated Circuits (18th : 2011 : Incheon)
dc.contributor.school School of Materials Science and Engineering
dc.identifier.doi http://dx.doi.org/10.1109/IPFA.2011.5992789
dc.description.version Accepted version
dc.identifier.rims 161597

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