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Electret mechanism, hysteresis, and ambient performance of sol-gel silica gate dielectrics in pentacene field-effect transistors

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Electret mechanism, hysteresis, and ambient performance of sol-gel silica gate dielectrics in pentacene field-effect transistors

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Title: Electret mechanism, hysteresis, and ambient performance of sol-gel silica gate dielectrics in pentacene field-effect transistors
Author: Cahyadi, Tommy; Tan, H. S.; Mhaisalkar, Subodh Gautam; Lee, Pooi See; Boey, Freddy Yin Chiang; Chen, Z. K.; Ng, C. M.; Rao, V. R.; Qi, Guojun
Copyright year: 2007
Abstract: The electret induced hysteresis was studied in sol-gel silica films that result in higher drain currents and improved device performance in pentacene field-effect transistors. Vacuum and ambient condition studies of the hysteresis behavior and capacitance-voltage characteristics on single layer and varying thicknesses of bilayer dielectrics confirmed that blocking layers of thermal oxide could effectively eliminate the electret induced hysteresis, and that thin (25 nm) sol-gel silica dielectrics enabled elimination of nanopores thus realizing stable device characteristics under ambient conditions.
Subject: DRNTU::Engineering::Materials
Type: Journal Article
Series/ Journal Title: Applied physics letters
School: School of Materials Science and Engineering
Rights: © 2007 American Institute of Physics. This paper was published in Applied Physics Letters and is made available as an electronic reprint (preprint) with permission of American Institute of Physics. The paper can be found at the following official URL: http://dx.doi.org/10.1063/1.2821377. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper is prohibited and is subject to penalties under law.
Version: Published version

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