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Fast analysis of a large-scale inductive interconnect by block-structure-preserved macromodeling

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Fast analysis of a large-scale inductive interconnect by block-structure-preserved macromodeling

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dc.contributor.author Yu, Hao
dc.contributor.author Chu, Chunta Lei He
dc.contributor.author Shi, Yiyu
dc.contributor.author Smart, David
dc.contributor.author He, Lei
dc.contributor.author Tan, Sheldon X. D.
dc.date.accessioned 2012-09-18T08:03:55Z
dc.date.available 2012-09-18T08:03:55Z
dc.date.copyright 2009
dc.date.issued 2012-09-18
dc.identifier.citation Yu, H., Chu, C. L. H., Shi, Y., Smart, D., He, L., & Tan, S. X. D. (2009). Fast analysis of a large-scale inductive interconnect by block-structure-preserved macromodeling. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(10), 1399-1411.
dc.identifier.issn 1063-8210
dc.identifier.uri http://hdl.handle.net/10220/8562
dc.description.abstract To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp inverse-inductance elements by replacing inductive-branch current with flux. The state matrix under VNA is diagonal-dominant, sparse, and passive. To further explore the sparsity and hierarchy at the block level, a new matrix-stretching method is introduced to reorder coupled fluxes into a decoupled state matrix with a bordered block diagonal (BBD) structure. A corresponding block-structure-preserved model-order reduction, called BVOR, is developed to preserve the sparsity and hierarchy of the BBD matrix at the block level. This enables us to efficiently build and simulate the macromodel within a SPICE-like circuit simulator. Experiments show that our method achieves up to 7× faster modeling building time, up to 33× faster simulation time, and as much as 67× smaller waveform error compared to SAPOR [a second-order reduction based on nodal analysis (NA)] and PACT (a first-order 2×2 structured reduction based on modified NA).
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on very large scale integration (VLSI) systems
dc.rights © 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/TVLSI.2009.2024343].
dc.title Fast analysis of a large-scale inductive interconnect by block-structure-preserved macromodeling
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TVLSI.2009.2024343

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