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Fast timing analysis of clock networks considering environmental uncertainty.

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Fast timing analysis of clock networks considering environmental uncertainty.

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dc.contributor.author Wang, Hai.
dc.contributor.author Yu, Hao.
dc.contributor.author Tan, Sheldon X. D.
dc.date.accessioned 2012-09-18T08:26:12Z
dc.date.available 2012-09-18T08:26:12Z
dc.date.copyright 2012
dc.date.issued 2012-09-18
dc.identifier.citation Wang, H., Yu, H., & Tan, S. X. D. (2012). Fast timing analysis of clock networks considering environmental uncertainty. Integration, the VLSI Journal, 45(4), 376-387.
dc.identifier.issn 0167-9260
dc.identifier.uri http://hdl.handle.net/10220/8563
dc.description.abstract Dynamic power management can significantly introduce environmental uncertainties such as non-uniform temperature gradients and supply voltage fluctuations. This can bring many challenges for the system-level timing verification such as for global clock networks. This paper presents a fast verification of clock-skew by an incremental-SVD-based compact modeling assisted with adaptive sampling. Firstly, an incremental-SVD is developed to perform an efficient update of environmental uncertainties avoiding a repeated full SVD. Secondly, an adaptive sampling is presented to build accurate models to sample clock and clock-skew for generating macromodels in a wide frequency range. Experiments on a number of clock networks show that when compared to the traditional fast TBR method, our macromodeling by incremental-SVD and adaptive sampling can significantly reduce the runtime with a similar accuracy. In addition, when compared to the Krylov-subspace-based method, our macromodeling further reduces the waveform error with a similar runtime.
dc.language.iso en
dc.relation.ispartofseries Integration, the VLSI journal
dc.rights © 2011 Elsevier. This is the author created version of a work that has been peer reviewed and accepted for publication by Integration, the VLSI journal, Elsevier. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: http://dx.doi.org/10.1016/j.vlsi.2011.03.001.
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title Fast timing analysis of clock networks considering environmental uncertainty.
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1016/j.vlsi.2011.03.001
dc.description.version Accepted version

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