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Effect of copper TSV annealing on via protrusion for TSV wafer fabrication

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Effect of copper TSV annealing on via protrusion for TSV wafer fabrication

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dc.contributor.author Heryanto, A.
dc.contributor.author Putra, W. N.
dc.contributor.author Trigg, Alastair David
dc.contributor.author Gao, S.
dc.contributor.author Kwon, W. S.
dc.contributor.author Che, Faxing
dc.contributor.author Ang, X. F.
dc.contributor.author Wei, J.
dc.contributor.author Made, Riko I.
dc.contributor.author Gan, Chee Lip
dc.contributor.author Pey, Kin Leong
dc.date.accessioned 2012-10-03T07:13:45Z
dc.date.available 2012-10-03T07:13:45Z
dc.date.copyright 2012
dc.date.issued 2012-10-03
dc.identifier.citation Heryanto, A., Putra, W. N., Trigg, A. D., Gao, S., Kwon, W. S., Che, F., et al. (2012). Effect of copper TSV annealing on via protrusion for TSV wafer fabrication. Journal of electronic materials, 41(9), 2533-2542.
dc.identifier.issn 0361-5235
dc.identifier.uri http://hdl.handle.net/10220/8698
dc.description.abstract Three-dimensional (3D) integrated circuit (IC) technologies are receiving increasing attention due to their capability to enhance microchip function and performance. While current efforts are focused on the 3D process development, adequate reliability of copper (Cu) through-silicon vias (TSVs) is essential for commercial high-volume manufacturing. Annealing a silicon device with copper TSVs causes high stresses in the copper and may cause a “pumping” phenomenon in which copper is forced out of the blind TSV to form a protrusion. This is a potential threat to the back-end interconnect structure, particularly for low-κ materials, since it can lead to cracking or delamination. In this work, we studied the phenomenon of Cu protrusion and microstructural changes during thermal annealing of a TSV wafer. The extruded Cu-TSV was observed using scanning electron microscopy (SEM), 3D profilometry, and atomic force microscopy (AFM). The electron backscatter diffraction (EBSD) technique was employed to study the grain orientation of Cu-TSV and evolution of the grain size as a function of annealing temperature. The elastic modulus and yield stress of copper were characterized using nanoindentation. A model for Cu protrusion is proposed to provide insight into the failure mechanism. The results help to solve a key TSV-related manufacturing yield and reliability challenge by enabling high-throughput TSV fabrication for 3D IC integration.
dc.language.iso en
dc.relation.ispartofseries Journal of electronic materials
dc.rights © 2012 TMS.
dc.subject DRNTU::Engineering::Materials
dc.title Effect of copper TSV annealing on via protrusion for TSV wafer fabrication
dc.type Journal Article
dc.contributor.school School of Materials Science and Engineering
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1007/s11664-012-2117-3

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